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lt3837 1 3837fa 47pf 2.2nf 10 22f 3k 22.1k 100k bas16 150k 12k 330 15 10 100nh 8m si7852dp si7336adp b0540w 1.37k 3.3nf 20k 1nf 1f 0.1f 0.1f 2.2nf bat54 osc v c fb uvlo pg sense + sense C sg sfst t on endly pgdly r cmp c cmp gnd v cc lt3837 86.6k ? 10f v in ?? 15k 10k 3837 ta01 ? 47f s 3 220f output 3.3v/10a 2n3906 fmmt718 fmmt618 typical application features applications description isolated no-opto synchronous flyback controller the lt ? 3837 is an isolated switching regulator controller designed for medium power ? yback topologies. a typical application is 10w to 60w with the part powered from a dc supply. the lt3837 is a current mode controller that regulates an output voltage based on sensing the secondary voltage via a transformer winding during ? yback. this allows for tight output regulation without the use of an optoisolator, improving dynamic response and reliability. synchronous recti? cation increases converter ef? ciency and improves output cross regulation in multiple output converters. the lt3837 operates in forced continuous conduction mode which improves cross regulation in multiple winding applications. switching frequency is user programmable and can be externally synchronized. the part also has load compensation, undervoltage lockout and soft-start circuitry. the lt3837 is available in a thermally enhanced 16-pin tssop package. 9v C18v to 3.3v at 10a isolated converter n senses output voltage directly from primary side windingno optoisolator required n synchronous driver for high ef? ciency n supply voltage range 4.5v to 20v n accurate regulation without user trims n programmable switching frequency from 50khz to 250khz n synchronizable n load compensation n undervoltage lockout n available in a thermally enhanced 16-lead tssop package n isolated medium power (10w to 60w) supplies n instrumentation power supplies n isolated medical supplies load current (a) 2 78 76 efficiency (%) 80 84 86 88 3 7 9 3837 ta01b 82 90 6 4 5 810 9v in 18v in load current (a) 3.00 output (v) 3.10 3.30 3.40 3.50 3.60 3837 ta01c 3.20 2 3 7 9 6 4 5 810 9v in 18v in ef? ciency vs load current regulation vs load current , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected b y u.s. patents includin g 6498466 , 5841643.
lt3837 2 3837fa electrical characteristics absolute maximum ratings v cc to gnd ................................................ C0.3v to 22v uvlo, sync pin voltage ............................C0.3v to v cc sense C , sense + pin voltage ...................... C0.5v, +0.5v fb pin current ........................................................2ma v c pin current ........................................................1ma operating junction temperature range (notes 2, 3) .......................................... C40c to 125c storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) .................. 300c (note 1) the l denotes speci? cations which apply over the full operating temperature range, otherwise speci? cations are t a = 25c. v cc = 14v; pg, sg open; v c = 1.4v, v sense = 0, r cmp = 1k, r ton = 90k, r pgdly = 27.4k, r endly = 90k, unless otherwise speci? ed. parameter conditions min typ max units power supply v cc operating range l 4.5 20 v v cc supply current (i cc ) (note 5) v c = open l 4 6.4 10 ma v cc shutdown current v c = open, v uvlo = ov l 50 150 a feedback ampli? er feedback regulation voltage (v fb ) l 1.220 1.237 1.251 v feedback pin input bias current r cmp open 200 na feedback ampli? er transconductance i c = 10 a l 700 1000 1400 mho feedback ampli? er source or sink current l 25 55 90 a feedback ampli? er clamp voltage v fb = 0.9 v fb = 1.4 2.56 0.84 v v reference voltage/current line regulation 12v v in 18v l 0.005 0.05 %v pin configuration fe package 16-lead plastic tssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 sg v cc t on endly sync sfst osc fb pg pgdly r cmp c cmp sense + sense C uvlo v c 17 t jmax = 125c, ja = 40c/w, jc = 10c/w exposed pad (pin 17) is gnd,must be soldered to pcb order information lead free finish tape and reel part marking package description temperature range lt3837efe#pbf lt3837efe#trpbf 3837efe 16-lead plastic tssop C40c to 125c lead based finish tape and reel part marking package description temperature range LLT3837EFE lt3837efe#tr 3837efe 16-lead plastic tssop C40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/
lt3837 3 3837fa note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. electrical characteristics the l denotes speci? cations which apply over the full operating temperature range, otherwise speci? cations are t a = 25c. v cc = 14v; pg, sg open; v c = 1.4v, v sense = 0, r cmp = 1k, r ton = 90k, r pgdly = 27.4k, r endly = 90k, unless otherwise speci? ed. note 3: the lt3837e is guaranteed to meet performance speci? cations from 0c to 85c. speci? cations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. note 4: t j is calculated from the ambient temperature t a and power dissipation pd according to the following formula: t j = t a + (p d ? 40c/w) note 5: supply current does not include gate charge current to the mosfets. see applications information. note 6: component value range guaranteed by design. parameter conditions min typ max units feedback ampli? er voltage gain v c = 1v to 2v 1400 v/v soft-start charging current v sfst = 1.5v 16 20 25 a soft-start discharge current v sfst = 1.5v, v uvlo = 0v 0.7 1.3 ma control pin threshold (v c ) duty cycle = min 1.0 v gate outputs pg, sg output high level pg, sg output low level l l 6.6 7.4 0.01 8.0 0.05 v v pg, sg output shutdown strength v uvlo = 0v; i pg , i sg = 20ma l 1.6 2.3 v pg rise time c pg = 1nf 11 ns sg rise time c sg = 1nf 15 ns pg, sg fall time c pg , c sg = 1nf 10 ns current ampli? er switch current limit at maximum v c v sense + l 88 98 110 mv v sense / v c 0.07 v/v sense voltage overcurrent fault voltage v sense +, v sfst < 1v 206 230 mv timing switching frequency (f osc )c osc = 100pf l 84 100 110 khz oscillator capacitor value (c osc ) (note 6) 33 200 pf minimum switch on time (t on(min) ) 200 ns flyback enable delay time (t ed ) 265 ns pg turn-on delay time (t pgdly ) 200 ns maximum switch duty cycle l 85 88 % sync pin threshold l 1.53 2.1 v sync pin input resistance 40 k load compensation load comp to v sense offset voltage v rcmp with v sense+ = 0 0.8 mv feedback pin load compensation current v sense + = 20mv 20 a uvlo function uvlo pin threshold (v uvlo ) l 1.215 1.240 1.265 v uvlo pin bias current v uvlo = 1.2v v uvlo = 1.3v C0.25 C4.50 0.1 C3.4 0.25 C2.50 a a
lt3837 4 3837fa temperature (c) C50 v cc current (a) 60 80 90 25 75 3837 g02 40 50 70 30 20 C25 0 50 100 125 10 0 v cc = 14v v uvlo = 0 temperature (c) C50 7 8 10 25 75 3837 g03 6 5 C25 0 50 100 125 4 3 9 i vcc (ma) dynamic current c pg c sg = 1nf, f osc = 100khz static part current v cc = 14v temperature (c) C50 90 sense voltage (mv) 92 96 98 100 110 104 0 50 75 3837 g04 94 106 108 102 C25 25 100 125 fb = 1.1v sense = v sense + with v sense C = 0v temperature (c) C50 v sense + C v sense C (mv) 215 25 3837 g05 200 190 C25 0 50 185 180 220 210 205 195 75 100 125 sense = v sense + with v sense C = 0v temperature (c) C50 90 f osc (khz) 92 96 98 100 110 104 0 50 75 3837 g06 94 106 108 102 C25 25 100 125 c osc = 100pf temperature (c) C50 1.230 v fb (v) 1.231 1.233 1.234 1.235 1.240 1.237 0 50 75 3837 g07 1.232 1.238 1.239 1.236 C25 25 100 125 temperature (c) C50 feedback pin input bias (na) 200 250 300 25 75 3837 g08 150 100 C25 0 50 100 125 50 0 temperature (c) C50 v fb reset (v) 1.03 25 3837 g09 1.00 0.98 C25 0 50 0.97 0.96 1.04 1.02 1.01 0.99 75 100 125 v fb (v) 0.9 C70 i vc (a) C50 C30 C10 70 30 1 1.1 1.4 50 10 1.2 1.3 1.5 3837 g10 125c 25c C40c typical performance characteristics v cc shutdown current vs temperature v cc current vs temperature sense voltage vs temperature sense fault voltage vs temperature oscillator frequency vs temperature v fb vs temperature feedback pin input bias vs temperature v fb reset vs temperature feedback ampli? er output current vs v fb
lt3837 5 3837fa temperature (c) C50 v uvlo (a) 0.70 0.80 0.90 0.85 25 75 3837 g15a 0.60 0.65 0.75 0.55 0.50 C25 0 50 100 125 0.45 0.40 v cc = 14v temperature (c) C50 i vc (a) 60 65 70 25 75 3837 g11 55 50 C25 0 50 100 125 45 40 source current v fb = 1.1v sink current v fb = 1.4v temperature (c) C50 900 g m (mho) 950 1000 1050 1100 C25 0 25 50 3837 g12 75 100 125 temperature (c) C50 uvlo (v) 1.240 1.245 1.250 25 75 3837 g14 1.235 1.230 C25 0 50 100 125 1.225 1.220 temperature (c) C50 3.4 3.5 3.7 25 75 3837 g15 3.3 3.2 C25 0 50 100 125 3.1 3.0 3.6 i uvlo (a) temperature (c) C50 sfst charge current (a) 23 25 3837 g16 20 18 C25 0 50 17 16 24 22 21 19 75 100 125 capacitance (nf) 0 time (ns) 80 70 60 50 40 30 20 10 0 8 3837 g17 246 10 7 135 9 t a = 25c fall time rise time temperature (c) C50 C25 19.0 v cc (v) 20.0 21.5 0 50 75 3837 g18 19.5 21.0 20.5 25 100 125 i cc = 10ma temperature (c) C50 a v (v/v) 1550 25 3837 g13 1400 1300 C25 0 50 1250 1200 1150 1100 1600 1650 1700 1500 1450 1350 75 100 125 typical performance characteristics feedback ampli? er source and sink current vs temperature feedback ampli? er g m vs temperature feedback ampli? er voltage gain vs temperature uvlo vs temperature i uvlo hysteresis vs temperature soft-start charge current vs temperature pg, sg rise and fall times vs load capacitance minimum on-time vs temperature uvlo shutdown threshold vs temperature
lt3837 6 3837fa temperature (c) C50 minimum enable time (ns) 220 240 260 25 75 3837 g21 200 180 C25 0 50 100 125 160 140 r endly = 90k temperature (c) C50 0 t pg (ns) 50 150 200 250 C10 30 50 383 7 g 2 0 100 C30 10 70 90 110 300 r pgdly = 16.7k r pgdly = 27.4k pin functions typical performance characteristics sg (pin 1): synchronous gate drive output. this pin pro- vides an output signal for a secondary-side synchronous switch. large dynamic currents may ? ow during voltage transitions. see the applications information for details. v cc (pin 2): supply voltage pin. bypass this pin to ground with a 4.7 f capacitor or more. t on (pin 3): pin for external programming resistor to set the minimum time that the primary switch is on for each cycle. minimum turn-on facilitates the isolated feedback method. see applications information for details. endly (pin 4): pin for external programming resistor to set enable delay time. the enable delay time disables the feedback ampli? er for a ? xed time after the turn-off of the primary-side mosfet. this allows the leakage inductance voltage spike to be ignored for ? yback voltage sensing. see applications information for details. sync (pin 5): pin for synchronizing the internal oscilla- tor with an external clock. the positive edge on a pulse causes the oscillator to discharge causing pg to go low (off) and sg high (on). the sync threshold is typically 1.4v. see applications information for details. tie to ground if unused. sfst (pin 6): this pin, in conjunction with a capacitor to ground, controls the ramp-up of peak primary current as sensed through the sense resistor. this is used to control converter inrush current at start-up. the v c pin voltage cannot exceed the sfst pin voltage, so as sfst increases, the maximum voltage on v c increases commensurately, allowing higher peak currents. total v c ramp time is ap- proximately 70ms per f of capacitance. leave pin open if not using the soft-start function. osc (pin 7): this pin in conjunction with an external capacitor de? nes the controller oscillator frequency. the frequency is approximately 100khz ? 100/c osc (pf). fb (pin 8): pin for the feedback node for the power sup- ply feedback ampli? er. feedback is sensed via a trans- former winding and enabled during the ? yback period. this pin also sinks additional current to compensate for load current variation as set by the r cmp pin. keep the thevenin equivalent resistance of the feedback divider at roughly 3k. v c (pin 9): pin used for frequency compensation for the switcher control loop. it is the output of the feedback ampli? er and the input to the current comparator. switcher frequency compensation components are normally placed on this pin to ground. the voltage on this pin is propor- tional to the peak primary switch current. the feedback ampli? er output is enabled during the synchronous switch on time. pg delay time vs temperature enable delay time vs temperature
lt3837 7 3837fa pin functions uvlo (pin 10): a resistive divider from v in to this pin sets an undervoltage lockout based upon v in level (not v cc ). when the uvlo pin is below its threshold, the gate drives are disabled, but the part draws its normal quiescent current from v cc . the v cc undervoltage lockout supersedes this function so v cc must be great enough to start the part. the bias current on this pin has hysteresis such that the bias current is sourced when the uvlo threshold is ex- ceeded. this introduces a hysteresis at the pin equivalent to the bias current change times the impedance of the upper divider resistor. the user can control the amount of hysteresis by adjusting the impedance of the divider. see the applications information for details. tie the uvlo pin to v cc if you are not using this function. sense C (pin 11), sense + (pin 12): these pins are used to measure primary side switch current through an external sense resistor. peak primary side current is used in the converter control loop. make kelvin connections to the sense resistor to reduce noise problems. sense C con- nects to the ground side. at maximum current (v c at its maximum voltage) it has a 98mv threshold. the signal is blanked (ignored) during the minimum turn-on time. c cmp (pin 13): pin for external ? lter capacitor for the optional load compensation function. load compensation reduces the effects of parasitic resistances in the feedback sensing path. a 0.1 f ceramic capacitor suf? ces for most applications. short this pin to gnd in less demanding ap- plications that dont require load compensation. r cmp (pin 14): pin for optional external load compensation resistor. use of this pin allows for nominal compensation of parasitic resistances in the feedback sensing path. in less demanding applications, this resistor is not needed and this pin can be left open. see applications informa- tion for details. pgdly (pin 15): pin for external programming resistor to set delay from synchronous gate turn-off to primary gate turn-on. see applications information for details. pg (pin 16): gate drive pin for the primary side mosfet switch. large dynamic currents ? ow during voltage transi- tions. see the applications information for details. gnd (exposed pad, pin 17): this is the ground connec- tion for both signal ground and gate driver grounds. this gnd should be connected to the pcb ground plane for electrical contact and rated thermal performance. careful attention must be paid to ground layout. see applications information for details.
lt3837 8 3837fa block diagram 11 sense C 12 sense + c cmp v cc 3v to fb pgate sgate current sense amp r cmpf 50k load compensation C + C + C + C + C + C + v cc 2 uvlo disable 0.8v 10 osc 7 t on 3 pgdly 15 endly 4 sync 5 1.25v reference (v fb ) internal regulator uvlo 3v 1.25v collapse detect error amp clamps 0.7 1.3 + C s r q q 1v 8 fb 9 v c 6 sfst tsd current trip slope compensation current comparator logic block C + C + 13 r cmp gate drive 14 pg 16 sg 1 gnd 17 oscillator set enable v cc gate drive + C overcurrent fault 3837 bd
lt3837 9 3837fa timing diagram flyback feedback amplifier s r q + C v fb 1.25v enable collapse detect 1v lt3837 feedback amp fb r1 r2 C + 8 9 v cc v in primary flyback secondary ? ? ? mp t1 v flbk ms c vc 3837 ffa c out isolated output primary side mosfet drain voltage pg voltage sg voltage v in v in t on enable delay min enable feedback amplifier enabled pg delay 3825 td v flbk 0.8 ? v flbk
lt3837 10 3837fa operation the lt3837 is a current mode switcher controller ic designed speci? cally for use in an isolated ? yback topology employing synchronous recti? cation. the lt3837 operation is similar to traditional current mode switchers. the major difference is that output voltage feedback is derived via sensing the output voltage through the transformer. this precludes the need of an optoisolator in isolated designs greatly improving dynamic response and reliability. the lt3837 has a unique feedback ampli? er that samples a transformer winding voltage during the ? yback period and uses that voltage to control output voltage. the internal blocks are similar to many current mode controllers. the differences lie in the ? yback feedback ampli? er and load compensation circuitry. the logic block also contains circuitry to control the special dynamic requirements of ? yback control. see application note 19 for more information on the basics of current mode switcher/controllers and isolated ? yback converters. feedback ampli? erpseudo dc theory for the following discussion refer to the simpli? ed flyback feedback ampli? er diagram. when the primary side mosfet switch mp turns off, its drain voltage rises above the v in rail. flyback occurs when the primary mosfet is off and the synchronous secondary mosfet is on. dur- ing ? yback the voltage on nondriven transformer pins is determined by the secondary voltage. the amplitude of this ? yback pulse as seen on the third winding is given as: v vi esrr n flbk out sec ds on sf = ++ () ? () r ds(on) = on resistance of the synchronous mosfet m s i sec = transformer secondary current esr = impedance of secondary circuit capacitor, winding and traces n sf = transformer effective secondary-to-feedback winding turns ratio (i.e., n s /n flbk ) the ? yback voltage is then scaled by an external resistive divider r1/r2 and presented at the fb pin. the feedback ampli? er then compares the voltage to the internal bandgap reference. the feedback amp is actually a transconductance ampli? er whose output is connected to v c only during a period in the ? yback time. an external capacitor on the v c pin integrates the net feedback amp current to provide the control voltage to set the current mode trip point. the regulation voltage at the fb pin is nearly equal to the bandgap reference v fb because of the high gain in the overall loop. the relationship between v flbk and v fb is expressed as: v rr r v flbk fb = + 12 2 ? combining this with the previous v flbk expression yields an expression for v out in terms of the internal reference, programming resistors and secondary resistances: v out = + ?? ? ? ? ? ? ? ?+ rr r vn i esrr fb sf sec ds on 12 2 C () ( () rearranging yields the equation for r1. rr vi esrr nv out sec ds on sf fb 12 1 =? +? + () () () ? ? () C ? ? ? ? ? ? ? the effect of nonzero secondary output impedance is dis- cussed in further detail; see load compensation theory. the practical aspects of applying this equation for v out are found in the applications information. feedback ampli? er dynamic theory so far, this has been a pseudo-dc treatment of ? yback feedback ampli? er operation. but the ? yback signal is a pulse, not a dc level. provision must be made to enable the ? yback ampli? er only when the ? yback pulse is present. this is accomplished by the enable line in the diagram. timing signals are then required to enable and disable the ? yback ampli? er. there are several timing signals which are required for proper lt3837 operation. please refer to the timing diagram.
lt3837 11 3837fa operation minimum output switch on-time (t on(min) ) the lt3837 affects output voltage regulation via ? yback pulse action. if the output switch is not turned on, there is no ? yback pulse and output voltage information is not available. this causes irregular loop response and start-up/latch-up problems. the solution is to require the primary switch to be on for an absolute minimum time per each oscillator cycle. if the output load is less than that developed under these conditions, forced continuous operation normally occurs. see applications information for further details. enable delay (endly) the ? yback pulse appears when the primary side switch shuts off. however, it takes a ? nite time until the trans- former primary side voltage waveform represents the output voltage. this is partly due to rise time on the pri- mary side mosfet drain node but, more importantly, is due to transformer leakage inductance. the latter causes a voltage spike on the primary side, not directly related to output voltage. some time is also required for internal settling of the feedback ampli? er circuitry. in order to maintain immunity to these phenomena, a ? xed delay is introduced between the switch turn-off command and the enabling of the feedback ampli? er. this is termed enable delay. in certain cases where the leakage spike is not suf? ciently settled by the end of the enable delay period, regulation error may result. see applications information for further details. collapse detect once the feedback ampli? er is enabled, some mechanism is then required to disable it. this is accomplished by a collapse detect comparator, which compares the ? yback voltage (fb referred) to a ? xed reference, nominally 80% of v fb . when the ? yback waveform drops below this level, the feedback ampli? er is disabled. minimum enable time the feedback ampli? er, once enabled, stays enabled for a ? xed minimum time period termed minimum enable time. this prevents lockup, especially when the output voltage is abnormally low; e.g., during start-up. the mini- mum enable time period ensures that the v c node is able to pump up and increase the current mode trip point to the level where the collapse detect system exhibits proper operation. this time is internally set. effects of variable enable period the feedback ampli? er is enabled during only a portion of the cycle time. this can vary from the ? xed minimum enable time described to a maximum of roughly the off switch time minus the enable delay time. certain parameters of ? yback amp behavior are directly affected by the variable enable period. these include effective transconductance and v c node slew rate. load compensation theory the lt3837 uses the ? yback pulse to obtain information about the isolated output voltage. an error source is caused by transformer secondary current ? ow through the synchronous mosfet r ds(on) and real life nonzero imped- ances of the transformer secondary and output capacitor. this was represented previously by the expression i sec ? (esr + r ds(on) ). however, it is generally more useful to convert this expression to effective output impedance. because the secondary current only ? ows during the off portion of the duty cycle (dc), the effective output imped- ance equals the lumped secondary impedance divided by off time dc. since the off time duty cycle is equal to 1 C dc then: r esr r dc s out ds on () () C = + 1 where: r s(out) = effective supply output impedance dc = duty cycle r ds(on) and esr are as de? ned previously this impedance error may be judged acceptable in less critical applications, or if the output load current remains relatively constant. in these cases the external fb resistive divider is adjusted to compensate for nominal expected error. in more demanding applications, output impedance error is minimized by the use of the load compensation function.
lt3837 12 3837fa operation t1 ? ? ? mp r cmpf 50k v in v flbk r2 load comp i r1 fb v fb q1 q2 r cmp c cmp r sense sense + 3837 f01 q3 C + a1 8 14 13 12 figure 1. load compensation diagram figure 1 shows the block diagram of the load compensa- tion function. switch current is converted to voltage by the external sense resistor, averaged and lowpass ? ltered by the internal 50k resistor r cmpf and the external capacitor on c cmp . this voltage is then impressed across the exter- nal r cmp resistor by op amp a1 and transistor q3. this produces a current at the collector of q3 that is subtracted from the fb node. this action effectively increases the voltage required at the top of the r1/r2 feedback divider to achieve equilibrium. the average primary side switch current increases to maintain output voltage regulation as output loading increases. the increase in average current increases the r cmp resistor current which affects a corresponding increase in sensed output voltage, compensating for the ir drops. assuming a relatively ? xed power supply ef? ciency, eff, power balance gives: p out = eff ? p in v out ? i out = eff ? v in ? i in average primary side current is expressed in terms of output current as follows: iki where k v veff in out out in = = 1 1 ? : ? so the effective change in v out target is: = vki r r rn thus v out out sense cmp sf out 11 ?? ?? : i i k r r rn out sense cmp sf = 11 ??? where: k1 = dimensionless variable related to v in , v out and ef? ciency as explained above r sense = external sense resistor nominal output impedance cancellation is obtained by equating this expression with r s(out) : k r r rn esr r dc sense cmp sf ds on 11 1 ??? C () = + solving for r cmp gives: rk rdc esr r rn cmp sense ds on sf = () + 1 1 1 ? ?C ?? () the practical aspects of applying this equation to determine an appropriate value for the r cmp resistor are found in the applications information.
lt3837 13 3837fa applications information primary winding feedback the previous work was developed using a separate wind- ing for voltage feedback. it is possible to use the primary winding as the feedback winding as well. this can simplify the design of the transformer. when using the primary winding the feedback voltage will be added to the v in voltage so: v vi esrr n flybk out out ds on sp = +? + () () where n sp is the transformer effective secondary to primary winding turns ratio. use the circuit of figure 2 to get more accurate output regulation. in this case the regulation equations becomes: r r v vi esrr n v fb out out ds on sp be 1 2 =? +? + () ? ? ? ? ? () ? ? ? ? ? where v be is the base emitter drop of the pnp (approxi- mately 0.7v). likewise the load compensation equation needs to be changed to use n sp instead of n sf so: rk rdc esr r rn cmp sense ds on sf = () + 1 1 1 ? ?C ?? () ? ms mp r2 r1 secondary primary c out v in v flybk 3837 f10 ? lt3837 fb pg figure 2
lt3837 14 3837fa applications information transformer design transformer design/speci? cation is the most critical part of a successful application of the lt3837. the following sections provide basic information about designing the transformer and potential tradeoffs. if you need help, the ltc applications group is available to assist in the choice and/or design of the transformer. turns ratios the design of the transformer starts with determining duty cycle (dc). dc impacts the current and voltage stress on the power switches, input and output capacitor rms currents and transformer utilization (size vs power). the ideal turns ratio is: n v v dc dc ideal out in = ? C 1 avoid extreme duty cycles as they, in general, increase current stresses. a reasonable target for duty cycle is 50% at nominal input voltage. for instance, if we wanted a 9v to 3.3v converter at 50% dc then: n ideal == 33 9 105 05 1 272 . ? C. .. in general, better performance is obtained with a lower turns ratio. a dc of 52% yields a 1:3 ratio. note the use of the external feedback resistive divider ratio to set output voltage provides the user additional freedom in selecting a suitable transformer turns ratio. turns ratios that are the simple ratios of small integers; e.g., 1:1, 2:1, 3:2 help facilitate transformer construction and improve performance. when building a supply with multiple outputs derived through a multiple winding transformer, lower duty cycle can improve cross regulation by keeping the synchronous recti? er on longer, and thus, keep secondary windings coupled longer. for a multiple output transformer, the turns ratio between output windings is critical and affects the accuracy of the voltages. the ratio between two output voltages is set with the formula v out2 = v out1 ? n21 where n21 is the turns ratio of between the two windings. also keep the secondary mosfet r ds(on) small to improve cross regulation. leakage inductance transformer leakage inductance (on either the primary or secondary) causes a spike after the primary side switch turn-off. this is increasingly prominent at higher load currents, where more stored energy is dissipated. higher ? yback voltage may break down the mosfet switch if it has too low a bv dss rating. one solution to reducing this spike is to use a snubber circuit to suppress the voltage excursion. however, sup- pressing the voltage extends the ? yback pulse width. if the ? yback pulse extends beyond the enable delay time, output voltage regulation is affected. the feedback system has a deliberately limited input range, roughly 50mv re- ferred to the fb node. this rejects higher voltage leakage spikes because once a leakage spike is several volts in amplitude, a further increase in amplitude has little effect on the feedback system. so it is advisable to arrange the snubber circuit to clamp at as high a voltage as possible, observing mosfet breakdown, such that leakage spike duration is as short as possible. application note 19 provides a good reference on snubber design. as a rough guide, total leakage inductances of several per- cent (of mutual inductance) or less may require a snubber, but exhibit little to no regulation error due to leakage spike behavior. inductances from several percent up to perhaps ten percent cause increasing regulation error. avoid double digit percentage leakage inductances as there is a potential for abrupt loss of control at high load current. this curious condition potentially occurs when the leakage spike becomes such a large portion of the ? yback waveform that the processing circuitry is fooled into thinking that the leakage spike itself is the real ? yback signal!
lt3837 15 3837fa applications information it then reverts to a potentially stable state whereby the top of the leakage spike is the control point, and the trailing edge of the leakage spike triggers the collapse detect circuitry. this typically reduces the output voltage abruptly to a fraction, roughly one-third to two-thirds of its correct value. once load current is reduced suf? ciently, the system snaps back to normal operation. when using transformers with considerable leakage inductance, exercise this worst-case check for potential bistability: 1. operate the prototype supply at maximum expected load current. 2. temporarily short-circuit the output. 3. observe that normal operation is restored. if the output voltage is found to hang up at an abnormally low value, the system has a problem. this is usually evident by simultaneously viewing the primary side mosfet drain voltage to observe ? rsthand the leakage spike behavior. a ? nal notethe susceptibility of the system to bistable behavior is somewhat a function of the load current/volt- age characteristics. a load with resistivei.e., i = v/r behavioris the most apt to be bistable. capacitive loads that exhibit i = v 2 /r behavior are less susceptible. secondary leakage inductance leakage inductance on the secondary forms an inductive divider on the transformer secondary, reducing the size of the feedback ? yback pulse. this increases the output voltage target by a similar percentage. note that unlike leakage spike behavior, this phenomenon is independent of load. since the secondary leakage in- ductance is a constant percentage of mutual inductance (within manufacturing variations), the solution is to adjust the feedback resistive divider ratio to compensate. winding resistance effects primary or secondary winding resistance acts to reduce overall ef? ciency (p out /p in ). secondary winding resistance increases effective output impedance degrading load regu- lation. load compensation can mitigate this to some extent but a good design keeps parasitic resistances low. bi? lar winding a bi? lar or similar winding is a good way to minimize troublesome leakage inductances. bi? lar windings also improve coupling coef? cients and thus improve cross regulation in multiple winding transformers. however, tight coupling usually increases primary-to-secondary capacitance and limits the primary-to-secondary break- down voltage, so it isnt always practical. primary inductance the transformer primary inductance, l p , is selected based on the peak-to-peak ripple current ratio (x) in the trans- former relative to its maximum value. as a general rule, keep x in the range of 50% to 70% ripple current (i.e., x = 0.5 to 0.7). higher values of ripple will increase conduction losses, while lower values will require larger cores. ripple current and percentage ripple is largest at minimum duty cycle; in other words, at the highest input voltage. l p is calculated from: l vdc fx p v p in max min osc max in in max = () = () () ? ?? ? 2 d dc eff fx p min osc max out () 2 ? ?? where: f osc is the osc frequency dc min is the dc at maximum input voltage x max is ripple current ratio at maximum input voltage continuing with the 9v to 3.3v example, let us assume a 10a output, 9v to 18v input power with 88% ef? ciency. using x = 0.7, and f osc = 200khz: p a w dc nv v in min in max out = ? = = + 33 10 88 37 5 1 1 . % . ? () = = + = = () 1 1 1 3 18 33 35 5 18 0 355 200 0 2 ? . .% ?. ?. l v khz p 7 7375 78 ?. . w h =
lt3837 16 3837fa applications information optimization might show that a more ef? cient solution is obtained at higher peak current but lower inductance and the associated winding series resistance. a simple spreadsheet program is useful for looking at tradeoffs. transformer core selection once l p is known, the type of transformer is selected. high ef? ciency converters use ferrite cores to minimize core loss. actual core loss is independent of core size for a ? xed inductance, but decreases as inductance increases. since increased inductance is accomplished through more turns of wire, copper losses increase. thus trans- former design balances core and copper losses. remem- ber that increased winding resistance will degrade cross regulation and increase the amount of load compensa- tion required. the main design goals for core selection are reducing copper losses and preventing saturation. ferrite core mate- rial saturates hard, rapidly reducing inductance when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and, consequently, out- put voltage ripple. do not allow the core to saturate! the maximum peak primary current occurs at minimum v in : i p vdc x now dc pk in in min max min ma =+ ? ? ? ? ? ? () ? ? : 1 2 x x in min out min nv v x v = + = + = = 1 1 1 1 1 3 9 33 52 4 ? ? . .% () i in min max osc p in dc flp kh () ? ?? ?. () = () 2 2 9052 200 z zhw ?. ? . . 7 8 37 5 0 380 = using the example numbers leads to: i w v a pk =+ ? ? ? ? ? ? = 37 5 9 0 524 1 0 380 2 947 . ?. ? . . multiple outputs one advantage that the ? yback topology offers is that ad- ditional output voltages can be obtained simply by adding windings. designing a transformer for such a situation is beyond the scope of this document. for multiple windings, realize that the ? yback winding signal is a combination of activity on all the secondary windings. thus load regulation is affected by each windings load. take care to minimize cross regulation effects. setting feedback resistive divider use the equation developed in the operation section for the feedback divider. it is recommended that the thevenin impedance of the resistors on the fb pin is roughly 3k for bias current cancellation and other reasons. for the example using primary winding sensing if esr = 0.002 and r ds(on) = 0.004 then: r k 1 3 1 237 3 3 10 0 002 0 004 13 =? +? + ( () () ? ? ? ? ? ? . ... / C C. . 0 7 22 75 ? ? ? ? ? ? ? ? = k so, choose 22.1k. current sense resistor considerations the external current sense resistor is used to control peak primary switch current, which controls a number of key converter characteristics including maximum power and external component ratings. use a noninductive current sense resistor (no wire-wound resistors). mounting the resistor directly above an unbroken ground plane con- nected with wide and short traces keeps stray resistance and inductance low. the dual sense pins allow for a fully kelvined connection. make sure that sense + and sense C are isolated and con- nect close to the sense resistor to preserve this. peak current occurs at 98mv of sense voltage v sense . so the nominal sense resistor is v sense /i pk . for example, a peak switch current of 10a requires a nominal sense resistor of 0.010 . note that the instantaneous peak power in the sense resistor is 1w, and that it is rated accordingly. the use of parallel resistors can help achieve low resistance, low parasitic inductance and increased power capability.
lt3837 17 3837fa applications information size r sense using worst-case conditions, minimum l p , v sense and maximum v in . continuing the example, let us assume that our worst-case conditions yield an i pk 10% above nominal so i pk = 10.41a . if there is a 5% tolerance on r sense and minimum v sense = 80mv, then r sense ? 105% = 88mv/10.41a and nominal r sense = 8.05m . round to the nearest available lower value 8.0m . selecting the load compensation resistor the expression for r cmp was derived in the operation section for primary winding sensing as: rk rdc esr r rn r cmp sense ds on sp = () + ?= 1 1 1 ? ?C ? () s s out () continuing the example: k v veff out in 1 33 988 0 417 = ? ? ? ? ? ? = () = = ? . % . if esr 0 0 002 0 004 0 417 80 1 .. .? .?C () = = and r r m ds on cmp 0 052 0 002 0 004 22 1 0 33 193 . .. ?. . . () + ? = k k this value for r cmp is a good starting point, but empiri- cal methods are required for producing the best results. this is because several of the required input variables are dif? cult to estimate precisely. for instance, the esr term above includes that of the transformer secondary, but its effective esr value depends on high frequency behavior, not simply dc winding resistance. similarly, k1 appears as a simple ratio of v in to v out times (differential) ef- ? ciency, but theoretically estimating ef? ciency is not a simple calculation. the suggested empirical method is as follows: 1. build a prototype of the desired supply including the actual secondary components. 2. temporarily ground the c cmp pin to disable the load compensation function. measure output voltage while sweeping output current over the expected range. approximate the voltage variation as a straight line, v out / i out = r s(out) . 3. calculate a value for the k1 constant based on v in , v out and the measured (differential) ef? ciency. 4. compute: rk r r r n orn cmp sense s out sp sf = 11 ??? () 5. verify this result by connecting a resistor of this value from the r cmp pin to ground. 6. disconnect the ground short to c cmp and connect the requisite 0.1 f ? lter capacitor to ground. measure the output impedance r s(out) = v out / i out with the new compensation in place. r s(out) should have decreased signi? cantly. fine tuning is accomplished experimentally by slightly altering r cmp . a revised estimate for r cmp is: =+ ? ? ? ? ? ? rr r r cmp cmp s out cmp s out ? () () 1 where r cmp is the new value for the load compensation resistor, r s(out)cmp is the output impedance with r cmp in place and r s(out) is the output impedance with no load compensation (from step 2). setting frequency the switching frequency of the lt3837 is set by an external capacitor connected between the osc pin and ground. recommended values are between 200pf and 33pf, yielding switching frequencies between 50khz and 250khz. figure 3 shows the nominal relationship between external capacitance and switching frequency. place the capacitor as close as possible to the ic and minimize osc trace length and area to minimize stray capacitance and potential noise pickup. you can synchronize the oscillator frequency to an external frequency. this is done with a signal on the sync pin. set the lt3837 frequency 10% slower than the desired external frequency using the osc pin capacitor, then use a pulse on the sync pin of amplitude greater than 2v and with the desired period. the rising edge of the sync signal initiates an osc capacitor discharge forcing primary mosfet off (pg voltage goes low). if the oscillator frequency is much different from the sync frequency, problems may occur
lt3837 18 3837fa applications information with slope compensation and system stability. keep the sync pulse width greater than 500ns. selecting timing resistors there are three internal one-shot times that are pro- grammed by external application resistors: minimum on-time, enable delay time and primary mosfet turn-on delay. these are all part of the isolated ? yback control technique, and their functions are previously outlined in the theory of operation section. the following information should help in selecting and/or optimizing these timing values. minimum on-time (t on(min) ) minimum on-time is the programmable period during which current limit is blanked (ignored) after the turn on of the primary side switch. this improves regulator performance by eliminating false tripping on the leading edge spike in the switch, especially at light loads. this spike is due to both the gate/source charging current and the discharge of drain capacitance. the isolated ? yback sensing requires a pulse to sense the output. minimum on-time ensures that there is always a signal to close the feedback loop. the lt3837 does not employ cycle skipping at light loads. therefore, minimum on-time along with synchronous recti? cation sets the switch over in forced continuous mode operation. the t on(min) resistor is set with the following equation: rk tns ton min on min () () () ()C . = 104 1 063 keep r ton(min) greater than 70k. a good starting value is 160k. enable delay time (endly) enable delay time provides a programmable delay between turn-off of the primary gate drive node and the subsequent enabling of the feedback ampli? er. as discussed earlier, this delay allows the feedback ampli? er to ignore the leakage inductance voltage spike on the primary side. the worst-case leakage spike pulse width is at maximum load conditions. so set the enable delay time at these conditions. while the typical applications for this part use forced continuous operation, it is conceivable that a secondary- side controller might cause discontinuous operation at light loads. under such conditions the amount of energy stored in the transformer is small. the ? yback waveform becomes lazy and some time elapses before it indicates the actual secondary output voltage. the enable delay time should be made long enough to ignore the irrelevant portion of the ? yback waveform at light load. even though the lt3837 has a robust gate drive, the gate transition-time slows with very large mosfets. increase delay time is as required when using such mosfets. the enable delay resistor is set with the following equation: rk tns endly endly () ()C . = 30 2 616 keep r endly greater than 40k. a good starting point is 56k. c oscap (pf) 30 50 f osc (khz) 100 200 300 100 200 3837 f02 figure 3. f osc vs osc capacitor values
lt3837 19 3837fa applications information primary gate delay time (pgdly) primary gate delay is the programmable time from the turn-off of the synchronous mosfet to the turn-on of the primary side mosfet. correct setting eliminates overlap between the primary side switch and secondary side synchronous switch(es) and the subsequent current spike in the transformer. this spike will cause additional component stress and a loss in regulator ef? ciency. the primary gate delay resistor is set with the following equation: rk tns pgdly pgdly () () . = + 47 901 a good starting point is 27k. soft-start functions the lt3837 contains an optional soft-start function that is enabled by connecting an external capacitor between the sfst pin and ground. internal circuitry prevents the control voltage at the v c pin from exceeding that on the sfst pin. there is an initial pull-up circuit to quickly bring the sfst voltage to approximately 0.8v. from there it charges to approximately 2.8v with a 20 a current source. the sfst node is then discharged to 0.8v when a fault occurs. a fault is v cc too low (undervoltage lockout), current sense voltage greater than 200mv or the ics thermal (overtemperature) shutdown is tripped. when sfst discharges, the v c node voltage is also pulled low to below the minimum current voltage. once discharged, the sfst recharges up again. in this manner, switch currents are reduced and the stresses in the converter are reduced during fault conditions. the time it takes to fully charge soft-start is: t cv a ms c f ss sfst sfst = = ?. ?() 14 20 70 uvlo pin function the uvlo pin provides a user programming undervoltage lockout. this is usually used to provide undervoltage lockout based on v in . the gate drivers are disabled when uvlo is below the 1.24v uvlo threshold. an external resistive divider between the input supply and ground is used to set the turn-on voltage. the bias current on this pin depends on the pin volt- age and uvlo state. the change provides the user with adjustable uvlo hysteresis. when the pin rises above the uvlo threshold a small current is sourced out of the pin, increasing the voltage on the pin. as the pin voltage drops below this threshold, the current is stopped, further dropping the voltage on uvlo. in this manner, hysteresis is produced. referring to figure 4, the voltage hysteresis at v in is equal to the change in bias current times r a . the design procedure is to select the desired v in referred voltage hysteresis, v uvhys . then: r v i a uvhys uvlo = where: i uvlo = i uvlol C i uvloh is approximately 3.4 a r b is then selected with the desired turn-on voltage: r r v v b a in on uvlo = ? ? ? ? ? ? () C1 v in r a lt3837 (3a) uv turning on uvlo i uvlo r b v in r a lt3837 (3b) uv turning off (3c) uv filtering uvlo uvl o r b v in r a2 r a1 c uvlo r b 3837 f03 i uvlo figure 4
lt3837 20 3837fa if we wanted a v in -referred trip point of 8.4v, with 0.3v of hysteresis (on at 8.4v, off at 8.1v): r v a kuse k r k v a = = = 03 34 88 2 86 6 86 6 84 124 . . ., . . . . b v v kuse k C ., 1 14 99 15 ? ? ? ? ? ? = even with good board layout, board noise may cause problems with uvlo. you can ? lter the divider but keep large capacitance off the uvlo node because it will slow the hysteresis produced from the change in bias current. figure 4c shows an alternate method of ? ltering by split- ting the r a resistor with the capacitor. the split should put more of the resistance on the uvlo side. control loop compensation loop frequency compensation is performed by connect- ing a capacitor network from the output of the feedback ampli? er (v c pin) to ground as shown in figure 5. be- cause of the sampling behavior of the feedback ampli? er, compensation is different from traditional current mode switcher controllers. normally only c vc is required. r vc can be used to add a zero but the phase margin improve- ment traditionally offered by this extra resistor is usually already accomplished by the nonzero secondary circuit impedance. c vc2 can be used to add an additional high frequency pole and is usually sized at 0.1 times c vc . applications information figure 5. v c compensation network 9 r vc v c c v c 3825 f05 c vc2 in further contrast to traditional current mode switchers, v c pin ripple is generally not an issue with the lt3837. the dynamic nature of the clamped feedback ampli? er forms an effective track/hold type response, whereby the v c voltage changes during the ? yback pulse, but is then held during the subsequent switch on portion of the next cycle. this action naturally holds the v c voltage stable during the current comparator sense action (current mode switching). an19 provides a method for empirically tweaking frequency compensation. basically, it involves introducing a load current step and monitoring the response. slope compensation this part incorporates current slope compensation. slope compensation is required to ensure current loop stability when the dc is greater than 50%. in some switcher con- trollers, slope compensation reduces the maximum peak current at higher duty cycles. the lt3837 eliminates this need by having circuitry that compensates for the slope compensation so that maximum current sense voltage is constant across all duty cycles. minimum load considerations at light loads, the lt3837 derived regulator goes into forced continuous conduction mode. the primary side switch always turns on for a short time as set by the t on(min) resistor. if this produces more power than the load requires, power will ? ow back into the primary during the off period when the synchronization switch is on. this does not produce any inherently adverse problems, though light load ef? ciency is reduced. maximum load considerations the current mode control uses the v c node voltage and ampli? ed sense resistor voltage as inputs to the current comparator. when the ampli? ed sense voltage exceeds the v c node voltage, the primary side switch is turned off. in normal use, the peak switch current increases while fb is below the internal reference. this continues until v c reaches its 2.56v clamp. at clamp, the primary side mosfet will turn off at the rated 98mv v sense level. this repeats on the next cycle. it is possible for the peak primary switch currents as referred across r sense to exceed the max 98mv rating because of the minimum switch on time blanking. if the voltage on v sense reaches 206mv after the minimum turn-on time, the sfst capacitor is discharged, which also discharges the v c capacitor. this then reduces the peak current on the next cycle and will reduce overall stress in the primary switch.
lt3837 21 3837fa applications information short-circuit conditions loss of current limit is possible under certain conditions such as an output short circuit. if the duty cycle exhib- ited by the minimum on-time is greater than the ratio of secondary winding voltage (referred-to-primary) divided by input voltage, then peak current is not controlled at the nominal value. it ratchets up cycle-by-cycle to some higher level. expressed mathematically, the requirement to maintain short-circuit control is: dc t f ir r vn min on min osc sc sec ds on in =< + () () () ? ? ? s sp where: t on(min) = primary side switch minimum on-time i sc = short-circuit output current other variables as previously de? ned. trouble is typically encountered only in applications with a relatively high product of input voltage times secondary- to-primary turns ratio and/or a relatively long minimum switch on time. additionally, several real world effects such as transformer leakage inductance, ac winding losses, and output switch voltage drop combine to make this simple theoretical calculation a conservative estimate. prudent design evaluates the switcher for short-circuit protection and adds any additional circuitry to prevent destruction. output voltage error sources the lt3837s feedback sensing introduces additional sources of errors. the following is a summary list. the internal bandgap voltage reference sets the reference voltage for the feedback ampli? er. the speci? cations detail its variation. the external feedback resistive divider ratio proportional directly affects regulated voltage. use 1% components. leakage inductance on the transformer secondary reduces the effective secondary-to-feedback winding turns ratio (n s /n f ) from its ideal value. this increases the output volt- age target by a similar percentage. since secondary leakage inductance is constant from part to part (with a tolerance) adjust the feedback resistor ratio to compensate. the transformer secondary current ? ows through the im- pedances of the winding resistance, synchronous mosfet r ds(on) and output capacitor esr. the dc equivalent current for these errors is higher than the load current because conduction occurs only during the converters off time. so divide the load current by (1 C dc). if the output load current is relatively constant, the feedback resistive divider is used to compensate for these losses. otherwise, use the lt3837 load compensation circuitry (see load compensation). if multiple output windings are used, the ? yback winding will have a signal that represents an amalgamation of all these windings impedances. take care that you examine worst-case loading conditions when tweaking the volt- ages. power mosfet selection the power mosfets are selected primarily on the criteria of on resistance r ds(on) , input capacitance, drain-to- source breakdown voltage (bv dss ), maximum gate voltage (vgs) and maximum drain current (i d(max) ). for the primary-side power mosfet, the peak current is: i i dc x pk out max min =+ ? ? ? ? ? ? 1 1 2 C ? where x is peak-to-peak current ratio as de? ned earlier. for each secondary-side power mosfet, the peak cur- rent is: i i dc x pk out max min =+ ? ? ? ? ? ? 1 1 2 C ? select a primary-side power mosfet with a b vdss greater than: bv i l c v v n dss pk lkg p in max out max sp ++ () ()
lt3837 22 3837fa where n sp re? ects the turns ratio of that secondary-to-pri- mary winding. l lkg is the primary-side leakage inductance and c p is the primary-side capacitance (mostly from the c oss of the primary-side power mosfet). a snubber may be added to reduce the leakage inductance spike as discussed earlier. for each secondary-side power mosfet, the bv dss should be greater than: bv dss v out + v in(max) ? n sp choose the primary side mosfet r ds(on) at the nominal gate drive voltage (7.5v). the secondary side mosfet gate drive voltage depends on the gate drive method. primary side power mosfet rms current is given by: i p vdc rmspri in in min max = () for each secondary-side power mosfet rms current is given by: i i dc rmssec out max = 1C calculate mosfet power dissipation next. because the primary-side power mosfet may operate at high v ds , a transition power loss term is included for accuracy. c miller is the most critical parameter in determining the transition loss, but is not directly speci? ed on the data sheets. c miller is calculated from the gate charge curve included on most mosfet data sheets (figure 6). applications information q a v gs ab 3825 f06 q b miller effect gate charge (q g ) figure 6. gate charge curve the ? at portion of the curve is the result of the miller (gate-to-drain) capacitance as the drain voltage drops. the miller capacitance is computed as: c qq v miller ba ds = C the curve is done for a given v ds . the miller capacitance for different v ds voltages are estimated by multiplying the computed c miller by the ratio of the application v ds to the curve speci? ed v ds . with c miller determined, calculate the primary-side power mosfet power dissipation: pi r v p dpri rms pri ds on in max in =+ () + () () () ( ? ? 2 1 m max in dr miller gate max th osc dc r c vv f ) () ?? C ? where: r dr is the gate driver resistance approximately 10 v th is the mosfet gate threshold voltage f osc is the operating frequency. (1 + ) is generally given for a mosfet in the form of a normalized rds(on) vs temperature curve. if you dont have a curve, use = 0.005/c as an estimate. the secondary-side power mosfets typically operate at substantially lower v ds , so you can neglect transition losses. the dissipation is calculated using: p d(sec) = i rms(sec) 2 ? r ds(on) (1 + ) with power dissipation known, the mosfets junction temperatures are obtained from the equation: t j = t a + p d ? ja where t a is the ambient temperature and ja is the mosfet junction to ambient thermal resistance. once you have t j , iterate your calculations recomputing , power dissipations until convergence. gate drive node consideration the pg and sg gate drivers are strong drives to minimize gate drive rise and fall times. this improves ef? ciency but the high frequency components of these signals can cause problems. keep the traces short and wide to reduce parasitic inductance.
lt3837 23 3837fa applications information the parasitic inductance creates an lc tank with the mosfet gate capacitance. in less than ideal layouts, a series resistance of 5 or more may help to dampen the ringing at the expense of slightly slower rise and fall times and ef? ciency. the lt3837 gate drives will clamp the max gate voltage to roughly 7.5v, so you can safely use mosfets with max v gs of 10v or larger. synchronous gate drive there are several different ways to drive the synchronous gate mosfet. full converter isolation requires the synchro- nous gate drive to be isolated. this is usually accomplished by way of a pulse transformer. usually the pulse driver is used to drive a buffer on the secondary as shown in the application on the front page of this data sheet. however, other schemes are possible. there are gate drivers and secondary side synchronous controllers avail- able that provide the buffer function as well as additional features. capacitor selection in a ? yback converter, the input and output current ? ows in pulses, placing severe demands on the input and output ? lter capacitors. the input and output ? lter capacitors are selected based on rms current ratings and ripple voltage. select an input capacitor with a ripple current rating greater than: i p v dc dc rms in in min max max = () C 1 continuing the example: i w v a rms == 37 5 9 1524 52 4 397 .C.% .% . input capacitor series resistance (esr) and inductance (esl) need to be small as they affect electromagnetic interference suppression. in some instances, high esr can also produce stability problems because ? yback converters exhibit a negative input resistance characteristic. refer to application note 19 for more information. the output capacitor is sized to handle the ripple current and to ensure acceptable output voltage ripple. the output capacitor should have an rms current rating greater than: ii dc dc rms out max max = 1C continuing the example :: ia a rms == 10 52 4 1524 10 5 .% C.% . this is calculated for each output in a multiple winding application. esr and esl along with bulk capacitance directly affect the output voltage ripple. the waveforms for a typical ? yback converter are illustrated in figure 7. output voltage ripple waveform secondary current primary current i pri $ v cout 3825 f07 ringing due to esl i pri n $ v esr figure 7. typical flyback converter waveforms the maximum acceptable ripple voltage (expressed as a percentage of the output voltage) is used to establish a starting point for the capacitor values. for the purpose of simplicity we will choose 2% for the maximum output ripple, divided equally between the esr step and the charging/discharging v. this percentage ripple changes, depending on the requirements of the application. you can modify the following equations. for a 1% contribution to the total ripple voltage, the esr of the output capacitor is determined by: esr vdc i cout out max out () 1 1 %? ?C
lt3837 24 3837fa applications information the other 1% is due to the bulk c component, so use: c i vf out out out osc 1% ? ? in many applications the output capacitor is created from multiple capacitors to achieve desired voltage ripple, reli- ability and cost goals. for example, a low esr ceramic capacitor can minimize the esr step, while an electrolytic capacitor satis? es the required bulk c. continuing our example, the output capacitor needs: esr v a m c a cout out () = 1 33 1 524 10 16 10 1 %? .?C.% . % %? . ? 3 3 200 1515 khz f = these electrical characteristics require paralleling several low esr capacitors possibly of mixed type. most capacitor ripple current ratings are based on 2000 hour life. this makes it advisable to derate the capacitor or to choose a capacitor rated at a higher temperature than required. one way to reduce cost and improve output ripple is to use a simple lc ? lter. figure 8 shows an example of the ? lter. r load c out2 1f v out c out 470f c1 47f s 3 from secondary winding l1 0.1h 3837 f08 figure 8 the design of the ? lter is beyond the scope of this data sheet. however, as a starting point, use these general guide lines. start with a c out 1/4 the size of the non? lter solution. make c1 1/4 of c out to make the second ? lter pole independent of c out . the smaller c1 may be best implemented with multiple ceramic capacitors. make l1 smaller than the output inductance of the transformer. in general, a 0.1 h ? lter inductor is suf? cient. add a small ceramic capacitor (c out2 ) for high frequency noise on v out . for those interested in more details refer to second-stage lc filter design, ridley, switching power magazine, july 2000, p8-10. circuit simulation is a way to optimize output capacitance and ? lters, just make sure to include the component parasitics. ltc switchercad? is a terri? c free circuit simulation tool that is available at www.linear.com. final optimization of output ripple must be done on a dedicated pc board. parasitic inductance due to poor layout can signi? cantly impact ripple. refer to the pc board layout section for more details. ic thermal considerations take care to ensure that the lt3837 junction temperature does not exceed 125c. power is computed from the aver- age supply current, the sum of quiescent supply current (i cc in the speci? cations) plus gate drive currents. the primary gate drive current is computed as: f osc ? q g where q g is the total gate charge at max v gs (obtained from the gate charge curve) and f is the switching frequency. since the synchronous driver is usually driving a capacitive load, the power dissipation is: f osc ? c s ? v sgmax where c s is the sg capacitive load and v sgmax is the sg pin max voltage. so total ic dissipation is computed as: p d(total) = v cc ? (i cc + f ?(q gpri + c s ? v sgmax )) v cc is the worst-case lt3837 supply voltage. junction temperature is computed as: t j = t a + p d ? ja where: t a is the ambient temperature ja is the fe16 package junction-to-ambient thermal impedance (40c/w). switchercad is a trademark of linear technology corporation.
lt3837 25 3837fa applications information pc board layout considerations in order to minimize switching noise and improve output load regulation, connect the gnd pin of the lt3837 directly to the ground terminal of the v cc decoupling capacitor, the bottom terminal of the current sense resistor, the ground terminal of the input capacitor, and the ground plane (multiple vias). place the v cc capacitor immediately adjacent to the v cc and gnd pins on the ic package. this capacitor carries high di/dt mosfet gate drive currents. use a low esr ceramic capacitor. take care in pcb layout to keep the traces that conduct high switching currents short, wide and with minimal overall loop area. these are typically the traces associated with the switches. this reduces the parasitic inductance and also minimizes magnetic ? eld radiation. figure 9 outlines the critical paths. keep electric ? eld radiation low by minimizing the length and area of traces (keep stray capacitances low). the drain of the primary side mosfet is the worst offender in this category. always use a ground plane under the switcher circuitry to prevent coupling between pcb planes. check that the maximum bv dss ratings of the mosfets are not exceeded due to inductive ringing. this is done by viewing the mosfet node voltages with an oscilloscope. if it is breaking down either choose a higher voltage device, add a snubber or specify an avalanche-rated mosfet. place the small-signal components away from high fre- quency switching nodes. this allows the use of a pseudo- kelvin connection for the signal ground, where high di/dt gate driver currents ? ow out of the ic ground pin in one direction (to the bottom plate of the v cc decoupling capacitor) and small-signal currents ? ow in the other direction. keep the trace from the feedback divider tap to the fb short to preclude inadvertent pickup. for applications with multiple switching power converters connected to the same input supply, make sure that the input ? lter capacitor for the ltc3837 is not shared with other converters. ac input current from another converter could cause substantial input voltage ripple and this could interfere with the lt3837 operation. a few inches of pc trace or wire (l ? 100nh) between the c in of the lt3837 and the actual source v in is suf? cient to prevent current sharing problems. figure 9. high current paths t2 t1 c r c vin ms mp gate turn-on gate turn-on r sense ?? c vcc sg v cc gnd lt3825 pg v cc v cc v cc v in gnd lt3825 gate turn-off gate turn-off q4 q3 c out 3837 f09 out ? ? ?
lt3837 26 3837fa 9v C 36v to 3.3v at 10a isolated converter ? ? 100k 10k 20 5 6 10 3.01k 1% 17.4k 1% 100k 1% 29.4k 1% 0.1f 10f si4896dy mmbt3904 bas70 7.5v 12k 1.37k 1% 150k v in 9v to 36v pa0184 si7336adp b0540w 2.2nf 47pf 0.1f 3.3nf 1nf t on sync pgdly uvlo sense C v c sense + r cmp endly osc lt3837 gnd sfst fb v cc sg sg pg c cmp bat54 10k 1nf 330 7 0.1f 15 1f 4.7 ? ? ? t1 t1 7/8/9 10/11/12 1/2 3/4 470pf 39 8m 20k sg 220f 6tpe220mi 47f s 3 0.1h fp2s-100-r v out 3.3v at 10a 3837 ta05 pin 2 to 4, 6t of 4 s 25awg pin 5 to 6, 7t of 32awg pin 10/11/12 to 7/8/9, 2t of 7mil c u foil pin 1 to 3, 6t of 4 s 25awg tape t1: efd20-3f3 (l p = 5h) typical application
lt3837 27 3837fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. fe16 (bc) tssop 0204 0.09 C 0.20 (.0035 C .0079) 0 C 8 0.25 ref 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 134 5 6 7 8 10 9 4.90 C 5.10* (.193 C .201) 16 1514 13 12 11 1.10 (.0433) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 2.94 (.116) 0.195 C 0.30 (.0077 C .0118) typ 2 recommended solder pad layout 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 2.94 (.116) 3.58 (.141) 3.58 (.141) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc package description fe package 16-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation bc
lt3837 28 3837fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt 0108 rev a ? printed in usa related parts part number description comments lt3825 isolated synchronous flyback controller with wide input supply range suitable for telecom or of? ine input voltage lt1424-5 isolated flyback switching regulator 5v output voltage, no optoisolator required lt1424-9 isolated flyback switching regulator 9v output voltage, regulation maintained under light loads lt1425 isolated flyback switching regulator no third winding or optoisolator required ltc1698 isolated secondary synchronous recti? er controller isolated power supplies, contains voltage merging, optocoupler driver , primary synchronization circuit lt1725 general purpose high power isolated flyback controller suitable for telecom or of? ine input voltage lt1737 high power isolated flyback controller powered from a dc supply voltage ltc1871 wide input range current mode no r sense ? controller 50khz to 1mhz, boost, flyback and sepic topology ltc3710 secondary side synchronous post regulator generates a regulated auxiliary output in isolated dc/dc converters. dual n-channel mosfet synchronous drivers lt3781/lt1698 36v to 72v input isolated dc/dc converter chipset synchronous operation: overvoltage/undervoltage protection, 10w t o 100w power supply, 1/2 to 1/4 brick footprint ltc3803 sot-23 flyback controller adjustable slope compensation, internal soft-start, 200khz ltc3806 synchronous flyback dc/dc controller medium power multiple outputs, 250khz soft-start no r sense is a trademark of linear technology corporation.

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